CLKDLL使用帶來的思考
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// BUFG : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (BUFG_inst) and/or the port declarations within the
// code : parenthesis may be changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.
// -----Cut code below this line---->
// BUFG: Global Clock Buffer (source by an internal signal)
// All FPGAs
// Xilinx HDL Language Template, version 9.1i
BUFG BUFG_inst (
.O(clk00), // Clock buffer output
.I(clk0) // Clock buffer input
);
// End of BUFG_inst instantiation
黃色：clk00 綠色：clkdv(2分頻時鐘)
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