信號名稱

位寬 bit

I/O

描述

Wr_vld_arb

1

寫DRAM控制器有效

Out_data_0

64

輸出至DRAM的data

Out_ctrl_0

8

輸出至DRAM德ctrl

Src_gen_seq

24

信源號、代的編號

Cam_vld

1

寫CAM控制器有效

Port_num_dram

2

數(shù)據(jù)的接收端口號

Out_data_1

64

輸出至output arbiter的data

Out_ctrl_1

8

輸出至output arbiter的ctrl

Wr_vld_1

1

輸出至output arbiter信號有效

信號名稱

位寬bits

I/O

描述

out_data_3

64

O

輸出至MAC層的數(shù)據(jù)總線

out_ctrl_3

8

O

輸出至MAC層的控制總線

out_wr_3

1

O

輸出有效

out_rdy_3

1

I

MAC層空閑標(biāo)志

dcod_data_0

64

I

已經(jīng)解碼的IP數(shù)據(jù)包的數(shù)據(jù)總線

dcod_ctrl_0

8

I

已經(jīng)解碼的IP數(shù)據(jù)包的控制總線

wr_vld_0

1

I

寫有效

wr_rdy_0

1

O

接收數(shù)據(jù)空閑標(biāo)志

non_ip_data

64

I

非IP數(shù)據(jù)包數(shù)據(jù)總線

non_ip_ctrl

8

I

非IP數(shù)據(jù)包控制總線

wr_vld_1

1

I

寫有效

wr_rdy_1

1

O

接收數(shù)據(jù)空閑標(biāo)志

信號名稱

位寬bits

I/O

描述

rd_dcod_reg_req_0

1

I

讀取解碼標(biāo)志位請求

rd_dcod_src_gen_0

12

I

要讀取的數(shù)據(jù)包的信源號和代編號

req_ack_vld_0

1

O

輸出有效

alredy_decod_0

1

O

解碼標(biāo)志（“1”代表已經(jīng)解碼，“0”代表未解碼）

rd_dcod_reg_req_1

1

I

讀取解碼標(biāo)志位請求

rd_dcod_src_gen_1

12

I

要讀取的數(shù)據(jù)包的信源號和代編號

req_ack_vld_1

1

O

輸出有效

alredy_decod_1

1

O

解碼標(biāo)志（為1時代表已經(jīng)解碼，為0時未解碼）

set_req

1

I

置位請求

set_src_gen

12

I

需要置位的數(shù)據(jù)包（表示已經(jīng)解碼完畢）

set_info_vld

1

I

置位信息有效

set_ack

1

O

置位請求響應(yīng)

reset_req

1

I

復(fù)位請求

reset_src_gen

12

I

需要復(fù)位的數(shù)據(jù)包（表示解碼后已發(fā)送完畢）

reset_info_vld

1

I

復(fù)位信息有效

reset_ack

1

O

復(fù)位請求響應(yīng)

Signal Group

Signal Name

Direction

Bits

Description

Request Negotiation

p_wr_req

from user logic to block-of-data rd/wr module

1

1=request for write transfer (data are from user logic to DRAM), 0=otherwise

Request Negotiation

p_wr_ptr

from user logic to block-of-data rd/wr module

PKT_MEM_PTR_WIDTH

the start address of DRAM for transfer. Each unit is 16-byte piece

Request Negotiation

p_wr_ack

from block-of-data rd/wr module to user logic

1

1=the arbiter acknowledges that the write requester can proceed, 0=otherwise

Data Transfer

p_wr_data_vld

from user logic to block-of-data rd/wr module

1

1=the write data is valid, 0=otherwise

Data Transfer

p_wr_data

from user logic to block-of-data rd/wr module

PKT_DATA_WIDTH

the data transferred from user logic to DRAM

Data Transfer

p_wr_full

from block-of-data rd/wr module to user logic

1

1=notify the user logic to pause transfer the next clock cycle until this signal is deasserted, 0=otherwise

Data Transfer

p_wr_done

from block-of-data rd/wr module to user logic

1

1=this is the last write and no more write will be accepted for this block-of-data, 0=otherwise

Signal Group

Signal Name

Direction

Bits

Description

Request Negotiation

p_rd_req

from user logic to block-of-data rd/wr module

1

1=request for read transfer (data are from DRAM to user logic), 0=otherwise

Request Negotiation

p_rd_ptr

from user logic to block-of-data rd/wr module

PKT_MEM_PTR_WIDTH

the start address of DRAM for transfer. Each unit is 16-byte piece

Request Negotiation

p_rd_ack

from block-of-data rd/wr module to user logic

1

1=the arbiter acknowledges that the read requester can proceed, 0=otherwise

Data Transfer

p_rd_rdy

from block-of-data rd/wr module to user logic

1

1=block-of-data rd/wr module has data for user logic to read, 0=otherwise

Data Transfer

p_rd_en

from user logic to block-of-data rd/wr module

1

1=user logic reads out one word of data from the block-of-data rd/wr module, 0=otherwise

Data Transfer

p_rd_data

from block-of-data rd/wr module to user logic

PKT_DATA_WIDTH

data transferred from block-of-data rd/wr module to user logic

Data Transfer

p_rd_done

from block-of-data rd/wr module to user logic

1

1=this is the last read data and no more data will be read for this block-of-data, 0=otherwise

信號名稱

位寬bits

I/O

描述

wr_vld_arb

1

I

Input_arbiter輸入有效

out_data_0

64

I

輸入的數(shù)據(jù)包的data_bus

out_ctrl_0

8

I

輸入數(shù)據(jù)包的ctrl_bus

port_num_dram

2

I

輸入信號的端口號，指明數(shù)據(jù)存放在DRAM的區(qū)域

wr_rdy_arb

1

O

寫空閑信號

port_num_rd

2

I

讀取數(shù)據(jù)包的區(qū)域

addr_vld

1

I

讀地址有效

block_num_rd

8

I

數(shù)據(jù)包存放的block的起始地址

rd_idle

1

O

讀空閑信號

in_rdy

1

I

數(shù)據(jù)輸出輸出允許信號

out_data

64

O

讀出的數(shù)據(jù)包的data_bus

out_ctrl

8

O

輸出數(shù)據(jù)包的ctrl_bus

data_vld

1

O

輸出數(shù)據(jù)有效

端口名稱

位寬 bits

I/O

描述

port_num_cam

2

In

數(shù)據(jù)寫入的CAM號，即信道號

Src_gen_seq

24

In

輸入數(shù)據(jù)包的信源號、代編號

Cam_vld

1

In

寫有效

Cam_rdy

1

Out

寫Cam準(zhǔn)備好

rd_idle

1

In

DRAM準(zhǔn)備好

block_num_rd

8

Out

讀DRAM的地址

addr_vld

1

Out

讀地址有效

port_num_rd

2

out

要讀取的DRAM的編號

Pkt_vld

1

Out

要解碼的數(shù)據(jù)包輸出有效標(biāo)志

Pkt_decoding

12

out

正在解碼的數(shù)據(jù)包的信源號、代編號

Decod_com

1

In

數(shù)據(jù)包解碼完成標(biāo)志

has_other_factor

1

Out

有另外一個解碼因子

Pkt_not_find

1

Out

所需要解碼數(shù)據(jù)包未找到

pkt_need_src_gen

12

In

解碼需要的數(shù)據(jù)包

need_pkt_vld

1

In

所需數(shù)據(jù)包有效

rd_dcod_reg_req_1

1

Out

讀解碼標(biāo)志寄存器請求

req_ack_vld_1

1

In

標(biāo)志位有效

Alredy_Decod_1

1

In

解碼標(biāo)志位

rd_dcod_src_gen_1

12

out

查詢數(shù)據(jù)包是否已經(jīng)解碼